The integrated circuit (IC) electronics industry is currently expending significant amounts of research money on improving the performance of ADCs telecommunication applications. Applications ranging from mobile communications to copper and fiber networks are requiring higher speeds and lower power. Pipeline ADC architectures are the most commonly chosen for these applications as they provide a good combination of high speed and low power. However, the most common pipeline ADCs must be preceded by a sample-and-hold-plus-amplifier (SHA) stage which significantly increases the amount of power required by the ADC. Extensive research efforts in IC pipeline ADC technology have been directed toward the goal of modifying the first pipeline stage so that it can also sample and hold the input signal, thereby avoiding the requirement for a separate input SHA stage, and eliminating its high power consumption.
The SHA stage preceding the first stage of a pipeline ADC is sometimes referred to as a track and hold (TH) stage. This is because it more accurately describes the process of tracking the analog input signal when charge storage devices, such as a plurality of sampling capacitors (CS) are connected to track the analog input signal in a TRACK mode, during a TRACK time interval, and then sampling the analog input signal in synchronization with an ADC SAMPLE CLK edge by holding a sample of the input signal on the sampling capacitors in a HOLD mode. That sample is then passed to the first stage of the several analog-to-digital conversion stages of the pipeline. The SHA stage often includes an additional amplifier, an input buffer amplifier (BAMP), which can buffer the ADC input to supply the large on-chip charge-discharge currents required by capacitors when tracking a fast, or high frequency, input signal.
One unfortunate characteristic of a high-speed TH or SHA input stage is that in order to not substantially degrade the signal-to-noise dynamic range (SNDR) characteristics of the subsequent pipeline stage, it must consume a high fraction of the total ADC power. Because the noise of either a TH or a pipeline ADC stage is inversely proportional to the size of the plurality of sampling capacitors in the stage, it is not unusual to find the value of the TH or SHA sampling capacitors to be twice the size of the capacitors in the first pipeline ADC stage. This large size is used to prevent the TH stage from significantly increasing the total ADC noise. However, because the power required to drive the TH CS is proportional to its size, the TH stage power often equals the total power of all the ADC pipeline stages.
A pipeline ADC first stage that includes the sample-and-hold or TH function is commonly known as an “SHA-less pipeline ADC first stage.” One such successful attempt to eliminate the input SHA has been disclosed in “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, December 2009, pp. 3305-3313, by Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, and Paul Wilkins. The Devarajan reference describes in detail the power savings that can be obtained by eliminating the input SHA stage, the problems that must be overcome, and the problems which remain that have not been overcome in their solution to the problem. It should be noted that this reference is the result of work on SHA-less pipeline ADC research by one of the leading companies in the field of high-speed analog to digital converters, and that this research work was published and considered to be original and significant by the leading journal for solid state circuits, namely, the IEEE Journal of Solid State Circuits.
The Devarajan reference describes several reasons why a common prior-art pipeline ADC first stage cannot be used to also perform the SH (or TH) function. With reference to prior-art FIG. 1a, and the remaining drawings, switch control signal names, such as PHI_1, are placed directly over the switch number callout, such as 111, to designate that switch 111 is controlled by logic signal PHI_1. In FIG. 1a, during TRACK the charging of Cs to the input voltage is possible because while the Cs input plates 152 are connected to VIN 151 through switch 111, controlled by logic signal PHI_1, the output plates 153_1 are connected to signal ground by switch 115a, controlled by logic signal PHI_1P. At the same time, the feedback capacitor CF is discharged and switchably connected to signal ground 153_2 by switch 116, controlled by logic signal PHI_1. During HOLD, switches 112T[1:16] and 112B[1:16] are controlled by logic signals PHI_2A and PHI_2B, respectively to connect the input plates 152 of Cs to positive or negative reference voltages VRP or VRN. However which ones of switches 112T and 112B are closed during HOLD are determined by the value of voltage VIN, which is quantized by a stack of a few capacitors in a flash ADC arrangement comprising a stage ADC, or SADC.
The residual charge error from the capacitor voltage switching process is amplified by the stage residue amplifier, or RAMP 118, with inputs INN 153_1 and INP 153_2, and positive output OUTP which produces residue output VRESIDUE on wire 161. The feedback capacitor CF 115 from the RAMP output 161 to input is usually set to achieve a precise low gain, such as 2, 4, or 8 by setting its value to the appropriate fraction of the total CS value. The combination of sampling, DAC, feedback capacitors, and RAMP is commonly referred to as the multiplying DAC, or MDAC, of the pipeline stage.
The Devarajan reference describes several reasons why the ADC first stage of FIG. 1a cannot be used to also perform the SH (or TH) function. One of the reasons is that after HOLD, when the switches 114[1:16] subsequently re-connect the Cs capacitors to the input in the next TRACK interval, they have stored a residual nonlinearly-quantized version of the previous input voltage and an error charge kick is given to the BAMP output. That output must rapidly settle to the new value of the input voltage. Any failure to achieve complete voltage settling results in a small nonlinear error. This error, whose value is computed in the Devarajan reference, is small but significant, and is proportional to the difference between the true value of the previous input voltage and the nonlinearly-quantized estimate of the previous input voltage.
The Devarajan reference also describes how the small nonlinear errors may be eliminated using another prior-art method. In that method (prior-art FIG. 1b.), the unit capacitors CS[1:16] 124_1 used to sample the input signal VIN 171 are separate from the DAC capacitors CDAC[1:16] 124_2 that are used to feed back a quantized approximation of the input signal. Because the capacitors are separate, the charge across CS[1:16] can be forced to zero during the entire HOLD half-clock cycle before being reconnected to the input during TRACK. This is accomplished by grounding the input side of CS using switch 125, controlled by logic level PHI1, while the other side of CS remains connected to ground through switch 123, controlled by PHI_1P during TRACK. The output terminal of feedback capacitor CF 125 is also reset as switch 126, controlled by PHI_1, connects it to ground 173_2 during TRACK.
During HOLD, amplifier 118 amplifies the difference voltage between INN 173_1 and INP 173_2 to produce a VRESIDUE voltage output on OUTP 181 with a forward gain determined by the ratio of feedback capacitor CF 125 to the input capacitors CS and CDAC. Unfortunately, for a given forward gain, the additional CDAC capacitors at the amplifier input increase the input capacitive load by approximately a factor of 2 as one plate remains connected to VRP or VRN by either switches 122T or 122B which are controlled by PHI_2A or PHI_2B during HOLD. The CDAC capacitors degrade the feedback loop gain approximately by a factor of 2. Therefore the amplifier then must be supplied twice as much power to regain the bandwidth lost by the loop gain degradation. Hence, the solution to the separating the CS and CDAC capacitors is not a viable low-power solution for high sample rate ADC applications.
The Devarajan reference describes a new low-power solution, shown in FIG. 2a, that uses just the input sampling capacitors 214[1:16] to combine the CS[1:16] and CDAC[1:16] functions shown in FIG. 1b. This solution purports to remove the residual CDAC charge by switchably connecting the input 252 of the sampling capacitors to ground 253_2 for a small portion of the clock half-cycle normally used for the signal-tracking (TRACK) time interval. Switches 212T, 212B, and 216 which are controlled by logic signals PHI_2A, PHI_2B, and in a PHI_1 function similar manner with similar timing to that already described for corresponding switches and logic signals in FIGS. 1a and 1b. The residue amplifier 218, with input INN 253_1, INP 253_2, OUT RESIDUE 261, and feedback capacitor CF 216 function in a similar manner to that already described for the corresponding amplifiers in FIGS. 1a and 1b. The switches 218[1:16] grounding the sampling capacitor input are driven by a short “clearing pulse” (PHI_CLEAR) which unfortunately consumes a portion of the TRACK half-clock interval prior to the time when switch 211, controlled by PHI_1, reconnects Cs to the input voltage VIN 251. During the time when switches 218[1:16] ground the sampling capacitor, switch 215 controlled by logic signal PHI_1P must remain on past the end of the HOLD period to insure that the switches 218 can reset the voltage across Cs to zero.
Although not discussed in the Devarajan reference, the amount of time allowed for the input capacitor to properly track the input signal is critical. The “substantially-shorter-than one-quarter clock interval” timing allocation for the clearing pulse must not overlap the TRACK interval and therefore must cause the beginning of the “shorter-than half-clock” TRACK interval to be delayed. Consequently, the BAMP driving the sampling capacitor is forced to have a shorter slew time and settling time. Shortening these times requires the BAMP to have higher bandwidth and therefore higher power. This limitation of the Devarajan reference, which is also common to any ADC using timing signals that are not at least a full one-half ADC sampling clock period in width for tracking, will be hereinafter referred to as the Shortened Tracking Time Limitation.
It is apparent that in the Devarajan reference, the input sampling capacitors are disconnected from the input buffer amplifier (BAMP) for a period of time greater than one half of the ADC sampling clock period. As is well understood by persons of ordinary skill in the design of operational amplifiers, if the ADC capacitive load on the BAMP is removed for a period of time, such as half an ADC sample clock period, the removal and consequently reduced capacitive load could lead to an instability which could cause either the output of an operational transconductance, or current-output BAMP (OTA) to begin uncontrolled oscillation for a brief period of time. To avoid the consequences of a reduced capacitive load, the BAMP can be designed to include additional output stabilization elements that would allow the capacitive load to be removed, but the added stabilization elements would also slow the time response of the amplifier. This limitation on input buffer amplifier design which arises when the output capacitive load is disconnected for a period of time such as a half-clock period, or more, will hereinafter be referred to as the ADC Input Capacitive Load Variation Limitation.
The time duration allowed to reset the input in the Devarajan reference cannot be arbitrarily shortened. Because the input sampling capacitor CS[1:16] 214[1:16] must be large enough to achieve acceptable ADC noise performance, the MOS switches 218[1:16] receiving the “clearing pulse” PHI_CLEAR must be quite large to short out the input in a time which is very small compared to the TRACK interval PHI_1. For the same reason switch 215, controlled by PHI_1P must also be large. Large devices have large parasitic junction capacitances with non-linear capacitance vs. voltage characteristics. Non-linear capacitances are well known contributors to high frequency amplifier distortion. Therefore the requirement to short out the input must not require a clearing switch that is unacceptably large in value. This requirement will be hereinafter referred to as the Clearing Switch Size Limitation, and that size limits the minimum width of the clearing pulse.
The Devarajan reference does describe how the time delay from sampling the final value of the input signal to the time that the comparators produce a reliable output adversely affects how the time available for the MDAC RAMP to fully settle is shortened. This adverse effect of the comparator time delay is to shorten the HOLD time interval. Any shortening of HOLD time available for MDAC output settling requires an increase in MDAC RAMP power to speed its response. Because the comparator delay must be kept to a small fraction of the HOLD clock width, higher ADC clock rates require shorter delay times, and consequently require that much higher power be supplied to the comparators so that they will more rapidly regenerate to a reliable answer. The effect of the comparator delay time in shortening the HOLD time available for MDAC output settling is hereinafter referred to as the Comparator Delay-Time Limitation.
The Devarajan reference qualitatively describes how the additional comparator power required to shorten the comparator delay time required to accommodate increasing ADC clock rates (shorter ADC clock periods) results in a significant sampling frequency limitation in SHA-less ADCs. The reference concludes that as required comparator power increases at some increasing-sample-rate total power inflection point, which is difficult to generally determine, it would be better to use an input SHA rather than an SHA-less configuration. As a result, the pipeline ADC in the Devarajan reference targets only a modest sampling rate of 125 mega-samples per second (MSPS) using 180 nm CMOS technology. Therefore, in order to allow a sufficient MDAC RAMP settling time, SADC power considerations prevent the comparator delay time from being reduced to an arbitrarily short value, in accordance with the above-described Comparator Delay-Time Limitation.
It is not unusual to find error rate requirements of less than 10E-15 in enterprise 10 giga-sample-per-second (GSPS) fiber optic or LAN communication systems. The major contributor to such error rates is the susceptibility of the comparator to what is commonly known as comparator metastability errors. Metastability errors can be reduced by allowing the comparators to have more time to regenerate, however, the minimum acceptable regeneration time is still a large multiple, such as 35 times the comparator basic regeneration time constant (τ). Even if τ is in the range of 30 picoseconds, typical of older technologies such as 180 mm, imposing a 35τ requirement for minimum delay time would consume an unacceptably-high fraction of the HOLD interval half-clock width when using the Devarajan circuit topology. Thus, the Comparator Delay-Time Limitation is a significant factor limiting sampling clock rates that must be considered in the design of any SHA-less ADC, particularly when sampling clock rates approach or exceed 1 GSPS.
If an input SHA stage is eliminated, and the input signal is not held, then the input signals may be changing rapidly at the time the first pipeline stage makes the transition from TRACK to HOLD. Therefore, the comparator stack comprising the SADC in the Devarajan reference must have fast input time-response characteristics similar to that of the BAMP charging CS. This requirement arises from the fact that although the SADC sample occurs at the same time as the input signal is sampled across CS, differences in the SADC input time response and the time response of the BAMP charging CS can result in SADC quantization error consuming an unacceptably large fraction of the MDAC error correction range. This limitation will be hereinafter referred to as the SADC-BAMP Bandwidth Matching Limitation.
The SADC-BAMP Bandwidth Matching Limitation becomes a severe limitation when the input signals have significant frequency components near the maximum bandwidth of the IC components used in the SADC-BAMP. For example, this matching limitation becomes severe when input signal bandwidths exceed 1 GHz and also in cases where multiple pipeline ADCs of lower bandwidth are interleaved to quantize higher bandwidth input signals. In such cases prior-art pipeline ADCs are preceded by an input SHA, despite its significantly higher power consumption. See, for example, “A 10.3 GS/s Gbit time-interleaved-pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS,” 2008 IEEE Symposium on VLSI Circuits, June 2008, pp. 18-19, by A. Nazemi, C. Grace, L. Lewyn, et. al.
The Devarajan reference also describes the requirement to reduce the 1/f noise contribution of the RAMP. It avoids the technique of auto-zeroing the amplifier to reduce 1/f noise because “auto-zeroing the amplifier can help reduce 1/f noise at the expense of increased complexity and power.” Unfortunately, most other methods are not nearly as effective as auto-zeroing for reducing 1/f noise. The 1/f noise limitation for an SHA-less pipeline ADCs without autozero, as described in the Devarajan reference, will hereinafter be referred to as the Partially-Corrected 1/f Noise Limitation.
It should be noted that the methods used to mitigate 1/f noise in the Devarajan reference rely simply on the use of large-gate-area PMOS devices and not on DC offset correction in the amplifier. DC offsets in amplifier topologies typical of the Devarajan reference are not corrected by additional circuitry commonly known as common-mode output DC feedback. That is because the common mode output voltage by definition has a value related only to the common mode voltage of the output voltage and not the differential offset components of the output voltage. DC offsets are becoming generally much larger as process variability affects device matching to a greater extent in deep-nanoscale CMOS technology nodes. The limitation of operating the RAMP with only common-mode DC offset correction, will be hereinafter referred to as the Amplifier Common-Mode Offset Correction Limitation, because this common-mode offset correction does not correct for input DC offsets. Additionally, because the Devarajan amplifier has a factor of 8 closed-loop forward gain, the DC output offset can be substantial, particularly in the case of deep-nanoscale CMOS nodes where process variability is a significant factor.
The Devarajan reference did not employ autozeroing as the preferred method for reducing 1/f noise or DC offset in a pipeline ADC stage for the complexity and power reasons previously stated. However, the prior art of U.S. Pat. No. 7,450,050, Nov. 11, 2008, by A. Rezayee, et. al. employed small autozeroing capacitors (CRESET_1 224-1 and CRESET_2 224-2 in FIG. 2b) and switches in an arrangement which add little complexity to the stage and, as stated in the patent, also consume little additional power. It should also be noted that although the Rezayee patent discloses an MDAC configuration that cannot be used directly as an SHA-less pipeline stage for the reasons previously stated in the Devarajan reference which pointed out the limitations of the prior art illustrated in FIG. 1a. However, the Rezayee patent circuit configuration achieves a significant bandwidth advantage over the MDAC of the Devarajan reference by pre-charging all the MDAC sampling capacitors CDAC_1P, CDAC_1N, 221-1, 221-2, CDAC_2P, CDAC_2N, 222-1, 222-2, and CF-1[1:2], 223-1[1:2], 223-2[1:2] to the input voltage difference INPV (250_1)−INNV (250_2) during TRACK (PHI_1), and then re-using some of the sampling capacitors CF-1[1:2], 223-1[1:2], 223-2[1:2] as RAMP feedback capacitors during HOLD (PHI_2). During HOLD (PHI_2), the input capacitors 221_1, 221_2 and 222_1, 222_2 are switchably connected to wither the positive or negative voltage references VRP or VRN using the same MDAC techniques described previously with reference to FIG. 1a. The bandwidth advantage in the Rezayee circuit configuration arises because half of the sampling capacitors (the CF capacitors) are removed from the input capacitive load during the HOLD timing interval. During the HOLD interval they are placed in the feedback path as they are connected to the positive and negative voltage outputs OUTPV 273_1 and OUTNV 273_2. Unlike the opamps in the previous figures, RAMP opamp 290 has separate positive and negative inputs INP 252_1 and INN 252_2, and separate positive and negative outputs OUTP and OUTN.
The Rezayee patent discloses a method of amplifier offset correction using switched capacitor techniques which is not a common-mode feedback method, but rather an autozero method. The method uses the switching of two small reset capacitors 224-1, 224-2 between RAMP input and output during TRACK (PHI_1) using switches 203-1, 203-2 and switches 206-1, 206-2, and then to two separate amplifier input and output common-mode voltage references VCM_IN 383 and VCM_OUT 289 using reset switches 205-1, 205-2 and 206-1, 206-2 during HOLD (PHI_2). The small autozero capacitors can be used to reset the pipeline stage and set the common-mode output voltage. While not greatly amplifying the input DC offset, unfortunately the amplifier input DC offset will still be present in the RAMP output after reset. With the advancement of CMOS technology line widths shrinking down into the deep nanoscale region, it is not unusual to find high speed operational amplifier input DC offsets in the range of several tens of millivolts. The accumulation of DC offset in a sequence of pipeline ADC stages is detrimental to the overall ADC performance because it subtracts from the available voltage headroom which, in turn, limits output signal swing. Input DC offset is not corrected at the opamp output in the Rezayee patent because the target output voltage is obtained by adding the same constant reference VCM_OUT-VCM_IN voltage difference 289-383 across the 2 small capacitors to the respective amplifier inputs. The limitation of the Rezayee patent RAMP which results in the DC output offset being equal to, or slightly greater than, the input DC offset of the input will be hereinafter referred to as the Uncorrected Amplifier DC Offset Limitation.
Another limitation of the Rezayee circuit arises from the connection of the two small reset capacitors 224-1, 224-2 to the amplifier inputs through switches 203-1, 203-2 during the PHI_1 time intervals when the MDAC stage is in TRACK. While it is important that switches 203-1, 203-2 are disconnected during the HOLD timing interval, it is well known that that CMOS switches exhibit a small parasitic load capacitance and additionally, a parasitic capacitance that couples one end of the switch to the other, even when the switch is open, or disconnected. It is therefore desirable to implement autozero-mode CMOS switched capacitor offset-cancellation circuits without requiring the switch devices to be connected directly to the charge-sensitive input of the amplifier. The limitation of the Rezayee patent autozero-mode offset-correction circuitry which results in the autozero circuitry to be connected directly to the residue amplifier input will be hereinafter referred to as the Autozero-Mode Amplifier Input Offset Switch Parasitic Capacitance Limitation.
When it is necessary to save pipeline ADC power by eliminating a separate input SHA stage, what is needed is therefore a pipeline ADC topology that achieves high speed operation and also overcomes the Shortened Tracking Time Limitation, the ADC Input Capacitive Load Variation Limitation, the Clearing Switch Size Limitation, the Comparator Delay-Time Limitation, the SADC-BAMP Bandwidth Matching Limitation, the Partially-Corrected 1/f Noise Limitation, the Amplifier Common-Mode Offset Correction Limitation, the Uncorrected Amplifier DC Offset Limitation, and the Autozero-Mode Amplifier Input Offset Switch Parasitic Capacitance Limitation. This invention provides such a SHA-less pipeline ADC topology.
What is needed for high sample-rate analog to digital conversion applications is therefore a new first-stage pipeline ADC topology that achieves significantly lower power by eliminating the separate SHA stage while overcoming all of the limitations previously described.